Field of the Invention
Embodiments of the present invention relate to a semiconductor device and particularly relates to a semiconductor device having an output buffer capable of impedance adjustment.
Description of Prior Art
A number of MOS transistors are used in semiconductor devices, such as RAM (Dynamic Random Access Memory). These MOS transistors are required to be able to operate at high speed with low operating voltage. To meet this requirement, MOS transistors with a low threshold voltage have come into wide use in these days. The MOS transistor with a low threshold voltage, however, produces a large leakage current (sub-threshold leakage current) when switched off, thus creating a demand for a reduction in such a sub-threshold leakage current.
Japanese Patent Application Laid-Open No. 2000-30443 and Japanese Patent Application Laid-Open No. 2000-195254 disclose an example of a technique for reducing a sub-threshold leakage current from a CMOS composed of MOS transistors with a low threshold voltage. FIG. 2 of Japanese Patent Application Laid-Open No. 2000-195254 depicts a technique of reducing a sub-threshold leakage current generated when the CMOS is in a stand-by mode by interposing a MOS transistor with a high threshold voltage between a power line and the source of an NMOS transistor or PMOS transistor making up the COM that switches off in the stand-by mode.
A certain type of a semiconductor device has an output buffer made up of a pull-up circuit and a pull-down circuit. Such an output buffer operates in such a way that when the output buffer outputs a high-voltage level signal, the pull-up circuit is switched on while the pull-down circuit is switched off and that when the output buffer outputs a low-voltage level signal, the pull-up circuit is switched off while the pull-down circuit is switched on. In its stand-by mode, the output buffer's pull-up circuit and pull-down circuit are both switched off, which gives the output terminal of the output buffer high impedance.
The pull-up circuit and the pull-down circuit are each composed of MOS transistors. There is a growing demand in recent years that using MOS transistors with a low threshold voltage as the pull-up circuit and pull-down circuit to realize a low operating voltage and a high operation speed. Therefore, for the output buffer, a technique for reducing a sub-threshold leakage current in the stand-by mode is in demand.